Embodiments of the present invention relate to memory devices, and more particularly to data transfer modes for memory devices.
In the conventional art, memory devices either transfer data synchronously or asynchronously. In asynchronous transfer, one device may initiate the transfer and wait until the another device responds. In synchronous transfer, the transfer occurs according to a clock signal that can be shared between two devices.
Referring to FIG. 1, a block diagram of an asynchronous memory device 100 in accordance with the conventional art is shown. The memory device 100 is comprised of an array of memory cells 105, a row address decoder 110, a column address decoder 115, sense amplifier and data-in driver 120, data buffer 125, and control logic 130. The control logic 130 receives various control signals 135, such as chip enable, output enable, write enable, and the like. The control logic 130 controls the state of the row decoder 110, column decoder 115, sense amplifier and data-in driver 120, and data buffer 125 in accordance with such control signals 135.
Addresses are received from an address bus 140 by the row and column decoders 110, 115. Typically, the lower address bits are decoded by the column decoder 115, while the upper address bits are decoded by the row decoder 110, or multiplexed addressing can be used. The output of the decoders 110, 115 select the appropriate wordlines (row) and bitlines (column) of the memory cell array 105.
During a write operation, the data buffer 125 can receive data from a data bus 145 to be written to a plurality of memory cells. The control logic 130 and data-in driver 120 provide the correct wordline and bitline biasing to perform a write operation to the memory cell selected by the row and column decoders 110, 115 and based upon the data values buffered by the data buffer 125.
During a read operation, the control logic 130 provides the correct wordline and bitline biasing for performing a read operation of the memory cell selected by the row and column decoders 110, 115. The sense amplifier 120 can detect a signal on the selected bitline and output an amplified signal to the data buffer 125 indicative of the programmed state of the memory cell. The data buffer 125 then drives the data bus 145 in accordance with the output from the sense amplifier 120.
Referring now to FIG. 2, a block diagram of a synchronous memory device 200 in accordance with the conventional art is shown. The memory device 200 is comprised of an array of memory cells 205, an address register 210, a row address decoder 215 and a column address decoder 220, sense amplifier and data-in driver 225, data register 230, data buffer 235, and control logic 240. The control logic 240 receives various control signals 245 such as chip enable, output enable, write enable, clock, and the like. The control logic 240 controls the state of the address register 210, row decoder 215, column decoder 220, sense amplifier and data-in driver 225, data register 230 and data buffer 235 in accordance with such control signals 245.
Addresses are received on an address bus 250 and loaded into the address register 210 according to a clock signal. The latched addresses are then decoded by the row and column decoders 215, 220. Typically the lower address bits are decoded by the column decoder 220, while the upper address bits are decoded by the row decoder 215. The output of the decoders selects the appropriate wordlines (row) and bitlines (column) of the memory cell array 205.
During a write operation, the data buffer 235 receive data to be written to a plurality of memory cells, which is latched by the data register 230 in accordance with a clock signal. The control logic 240 and data-in driver 225 provide the correct wordline and bitline biasing to perform a write operation to the memory cell selected by the row and column decoders 215, 200 and based upon the latched data values.
During a read operation, the control logic 225 provides the correct wordline and bitline biasing for performing a read operation of the memory cell selected by the row and column decoders 215, 220. The sense amplifier 225 detects a signal on the selected bitline and outputs a signal to the data register 230 indicative of the programmed state of the memory cell. The data register 230 latches the signal from the sense amplifier 225 and then provides the data to the data buffer 235 in accordance with a clock signal. The data buffer 235 then drives a data bus 255 based upon such data values.
Accordingly, memory devices according to the conventional art are disadvantageous in that they typically only provide a single mode of data transfer. That is, memory devices according to the conventional art typically either provide for only asynchronous data transfer or only synchronous data transfer.
Embodiments of the present invention provide a memory device having multiple modes of data transfer. Embodiments of the present invention provide for asynchronous data transfer. Embodiments of the present invention provide for synchronous data transfer.
Embodiments of the present invention provide multiple modes of data transfer utilizing async/sync logic and a configuration register. The async/sync logic utilizes the configuration register and various control signals to determine whether a data transfer operation should be asynchronous or synchronous. The async/sync logic also utilizes the configuration register and various control signals to determiner other functionalities of the particular data transfer mode. Functionalities of a data transfer mode may include normal and page mode, page length, burst read, linear or interleaved burst, burst wrap, burst suspend, data hold length, first access latency, transition between synchronous and asynchronous mode, and the like.
Accordingly, the multiple modes of data transfer provided by embodiments of the present invention advantageously allow for replacing NOR-flash memory devices with NAND-flash memory devices. Embodiments of the present invention are also advantageous in that the memory device may be operated as a read through device.